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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The open ISA philosophy and the standardization landscape of RISC-V International.
- Understanding the RISC-V mental model: Load-Store architecture, register file structure, and byte ordering.
- Comparative analysis with ARM, x86, and POWER architectures to evaluate trade-offs for heterogeneous computing designs.
- Assessing ecosystem maturity, including contributions from SiFive, T-Head, Western Digital, and the expanding open-source silicon community.
- Standardized interfaces: RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL).
Memory Models and ABI Compliance
- Unprivileged Architecture specification: CSR mapping, exception handling mechanisms, and memory hierarchies.
- RV32I/RV64I instruction sets and ABI compliance to ensure cross-platform binary portability.
- Memory ordering conventions and barrier instructions tailored for multiprocessor systems.
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions.
- Bitness-aware programming strategies for both 32-bit and 64-bit RISC-V targets.
- Calling conventions and stack frame management essential for embedded and real-time software systems.
Compiler Toolchain Proficiency
- Mastery of the LLVM-based compiler toolchain: utilizing Clang, LLVM, and Binutils for RISC-V cross-compilation.
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments.
- Leveraging compiler intrinsics, optimizing code through various optimization levels, and applying profiling-driven tuning techniques.
- Workflows for open-source toolchain development: building, testing, and packaging custom GCC/Clang toolchains.
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: harnessing zero-cost abstractions, unsafe memory management, and bare-metal development.
- Navigating No-Std environments: implementing custom linkers, developing device drivers, and managing memory-mapped I/O.
- Developing BSPs for Zephyr RTOS and Buildroot on RISC-V targets.
- Peripheral interfacing techniques covering GPIO, I2C, SPI, UART, and DMA controller programming.
Power and Performance Optimization
- Strategies for clock gating, power domain management, and optimizing low-power modes.
- Cycle-accurate performance analysis using simulation profilers and hardware performance counters.
- Tuning real-time interrupt latency for safety-critical applications.
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Implementing OpenSBI (SBI specification) for bootloader firmware development.
- Deploying UEFI/EDK II on RISC-V for modern firmware boot stack development.
- Porting Coreboot and U-Boot to RISC-V single-board computers.
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: device tree overlays, CPU topology management, and interrupt controller (AIA) driver development.
- Developing vendor BSPs and configuring kernels for custom SoC platforms.
- Implementing file system support, networking stacks, and containerization capabilities (Docker, Kubernetes) on RISC-V host systems.
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Design methodologies for Network-on-Chip (NoC) in RISC-V multi-core processors.
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols.
- Integrating open-source IP sources like OpenCores and the ChIPS Framework, alongside vendor RTL components.
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe).
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores on FPGA, such as BOOM, VexRiscv, and PULP.
- Applying SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies.
- Utilizing formal verification tools and property-based testing for rigorous RISC-V core validation.
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Exploring vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration.
- Leveraging variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution.
- Utilizing vector mask operations, segment control, and data type flexibility to support DSP and ML workloads.
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators through custom extensions and CBAR-based operand interfaces.
- Modifying compiler frontends for custom instruction generation and efficient code emission.
- Developing hardware-software partitioning strategies for integrating accelerators into production SoCs.
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units featuring systolic arrays, tensor cores, and weight compression techniques for on-chip AI acceleration.
- Applying model quantization methods (INT8, INT4, FP8) to enable edge deployment on RISC-V platforms.
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets.
Heterogeneous Computing for AI Workloads
- Co-designing the interaction between RISC-V host CPUs and AI accelerator NPUs to support real-time inference pipelines.
- Optimizing the memory subsystem, including HBM/DDR bandwidth management for ML model weights and activations.
- Managing thermal and power budgets within edge AI inference systems.
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms.
- Architecting Secure Enclaves/TEEs for RISC-V, including OP-TEE integration and SEV-class trusted execution environments.
- Ensuring boot chain security through root of trust establishment, secure boot processes, and measured launch attestation.
Cryptographic Acceleration
- Leveraging RISC-V cryptographic extensions (Zk, Zkr, K) to accelerate SHA, AES, RSA, RSA-PSS, and ECC operations.
- Integrating post-quantum cryptography (PQC) solutions for next-generation RISC-V processors.
- Mitigating side-channel attack techniques through constant-time programming, masking strategies, and hardware random number generators.
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastery of ISA extension design methodology: encoding, encoding tables, ABI impact analysis, and the RISC-V International specification submission process.
- Designing custom register files utilizing CBAR (Custom Base Address Registers) for operand dispatch.
- Implementing instruction pipelining, hazard detection mechanisms, and pipeline modifications for custom extensions.
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions, employing both directed and constraint-random stimulus generation.
- Establishing regression testing frameworks and adopting coverage-driven verification practices for architectural modifications.
- Conducting interoperability testing to ensure custom instructions operate correctly within established ABI constraints.
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors.
- Defining ASIL-Q classification levels and developing safety manuals for RISC-V silicon IP.
- Implementing deterministic interrupt handling, lockstep core pairs, and robust memory protection for safety-critical RISC-V systems.
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and implementing deterministic scheduling on RISC-V multicore platforms.
- Developing Industrial IoT gateways using RISC-V, focusing on connectivity, edge analytics, and OTA firmware update systems.
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: Designing ISA extensions and core configurations for a defined use case.
- RTL implementation in SystemVerilog, accompanied by UVM testbenches and formal verification coverage.
- FPGA prototyping, boot firmware development, and bare-metal driver stack integration.
- Customizing the Linux BSP and toolchain for the custom RISC-V core.
- AI workload deployment: Integrating NPUs, performing model quantization, and conducting performance benchmarking.
- Security validation: Enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration.
- Producing technical architecture documentation, analyzing IP strategy, and delivering a cross-functional team presentation.
Requirements
None.
21 Hours
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- Customized Content: We adapt the syllabus and practical exercises to the real goals and needs of your project.
- Flexible Schedule: Dates and times adapted to your team's agenda.
- Format: Online (live), In-company (at your offices), or Hybrid.
Price per private group, online live training, starting from 4800 € + VAT*
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Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
