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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- Open ISA philosophy and the RISC-V International standardization landscape
- Mental Model of RISC-V: Load-Store Architecture, Register File, Byte Ordering
- Comparison with ARM, x86, and POWER: Trade-offs for heterogeneous computing architectures
- Ecosystem maturity assessment: SiFive, T-Head, Western Digital, and the growing open-source silicon community
- Standardized interfaces: RISC-V Privileged ISA, Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specification: CSR map, exception handling, and memory hierarchies
- RV32I / RV64I instruction sets and ABI compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), Atomic operations (A) extensions
- Bitness-aware programming strategies for 32-bit and 64-bit RISC-V targets
- Calling conventions and stack frame management for embedded and real-time software systems
Compiler Toolchain Proficiency
- LLVM-based compiler toolchain: Clang, LLVM, Binutils for RISC-V cross-compilation
- Linker scripts, sections, and memory layout configuration for bare-metal and RTOS environments
- Compiler intrinsics, optimization levels, and profiling-driven code tuning
- Open-source toolchain development workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: zero-cost abstractions, unsafe memory management, and bare-metal development
- No-Std environments: custom linkers, device driver development, and memory-mapped I/O
- Zephyr RTOS and Buildroot BSP development for RISC-V targets
- Peripheral interfacing: GPIO, I2C, SPI, UART, and DMA controller programming
Power and Performance Optimization
- Clock gating, power domain management, and low-power mode optimization
- Cycle-accurate performance analysis with simulation profilers and hardware performance counters
- Real-time interrupt latency tuning for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI (SBI specification implementation): bootloader firmware development
- UEFI/EDK II on RISC-V: modern firmware boot stack development
- Coreboot and U-Boot porting for RISC-V single-board computers
Linux Kernel Integration
- RISC-V mainline kernel contributions: device tree overlays, CPU topology, and interrupt controller (AIA) driver development
- Vendor BSP development and kernel configuration for custom SoC platforms
- File system support, networking stack, and containerization support (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Axi4/CHI cache coherence and inter-processor communication protocols
- Open-source IP integration: OpenCores, ChIPS Framework, and vendor RTL components
- Bus matrix design and memory controller integration (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- FPGA synthesis and implementation of RISC-V core (e.g., BOOM, VexRiscv, PULP)
- SystemVerilog Assertions (SVA) and UVM-based functional verification methodology
- Formal verification tools and property-based testing for RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Vector load/store, vector-fused multiply-add (VFMA), and matrix computation acceleration
- Variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
- Vector mask operations, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators through custom extensions and CBAR-based operand interfaces
- Compiler frontend modifications for custom instruction generation and code emission
- Hardware-software partitioning strategies for accelerator integration in production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Neural Processing Unit architecture: systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
- Framework compatibility: TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-design of RISC-V host CPU with AI accelerator NPU for real-time inference pipelines
- Memory subsystem optimization: HBM/DDR bandwidth management for ML model weights and activations
- Thermal and power budgeting for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Secure Enclave/TEE architectures for RISC-V: OP-TEE integration, SEV-class trusted execution environments
- Boot chain security: root of trust, secure boot, and measured launch attestation
Cryptographic Acceleration
- RISC-V cryptographic extensions (Zk, Zkr, K extensions): SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Post-quantum cryptography (PQC) integration for next-generation RISC-V processors
- Side-channel attack mitigation techniques: constant-time programming, masking, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design methodology: encoding, encoding tables, ABI impact analysis, and RISC-V International specification submission process
- Custom register file design with CBAR (Custom Base Address Registers) for operand dispatch
- Instruction pipelining, hazard detection, and pipeline modifications for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Testbench design for custom extensions: directed vs. constraint-random stimulus generation
- Regression testing frameworks and coverage-driven verification for architectural modifications
- Interoperability testing: ensuring custom instructions function within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- ISO 26262 functional safety compliance for RISC-V automotive processors
- ASIL-Q classification and safety manual development for RISC-V silicon IP
- Deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Industrial IoT gateway development with RISC-V: connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: ISA extensions and core configuration design for a defined use case
- RTL implementation in SystemVerilog with UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Linux BSP and toolchain customization for the custom RISC-V core
- AI workload deployment: NPU integration, model quantization, and performance benchmarking
- Security validation: PMP enforcement, secure boot, and cryptographic acceleration benchmarking
- Technical architecture documentation, IP strategy analysis, and cross-functional team presentation
21 Hours
Custom Corporate Training
Training solutions designed exclusively for businesses.
- Customized Content: We adapt the syllabus and practical exercises to the real goals and needs of your project.
- Flexible Schedule: Dates and times adapted to your team's agenda.
- Format: Online (live), In-company (at your offices), or Hybrid.
Price per private group, online live training, starting from 4800 € + VAT*
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Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
